The present invention relates to flip chip packaging of semiconductor integrated circuits. More particularly, the present invention relates to new and improved bump pad designs for securing a solder bump to an IC chip in flip chip packaging technology.
One of the last processes in the production of semiconductor integrated circuits (IC) is multi-leveled packaging, which includes expanding the electrode pitch of the IC chips containing the circuits for subsequent levels of packaging; protecting the chip from mechanical and environmental stress; providing proper thermal paths for channeling heat dissipated by the chip; and forming electronic interconnections. The manner in which the IC chips are packaged dictates the overall cost, performance, and reliability of the packaged chips, as well as of the system in which the package is applied.
Package types for IC chips can be broadly classified into two groups: hermetic-ceramic packages and plastic packages. A chip packaged in a hermetic package is isolated from the ambient environment by a vacuum-tight enclosure. The package is typically ceramic and is utilized in high-performance applications. A chip packaged in a plastic package, on the other hand, is not completely isolated from the ambient environment because the package is composed of an epoxy-based resin. Consequently, ambient air is able to penetrate the package and adversely affect the chip over time. Recent advances in plastic packaging, however, has expanded their application and performance capability. Plastic packages are cost-effective due to the fact that the production process is typically facilitated by automated batch-handling.
A recent development in the packaging of IC chips is the ball grid array (BGA) package, which may be utilized with either ceramic packages or plastic packages and involves different types of internal package structures. The BGA package uses multiple solder balls or bumps for electrical and mechanical interconnection of IC chips to other microelectronic devices. The solder bumps serve to both secure the IC chip to a circuit board and electrically interconnect the chip circuitry to a conductor pattern formed on the circuit board. The BGA technique is included under a broader connection technology known as xe2x80x9cControlled Collapse Chip Connection-C4xe2x80x9d or xe2x80x9cflip-chipxe2x80x9d technology.
Flip chip technology can be used in conjunction with a variety of circuit board types, including ceramic substrates, printed wiring boards, flexible circuits, and silicon substrates. The solder bumps are typically located at the perimeter of the flip chip on electrically conductive bond pads that are electrically interconnected with the circuitry on the flip chip. Because of the numerous functions typically performed by the micro-circuitry of a flip chip, a relatively large number of solder bumps are often required. The size of a flip chip is typically on the order of about thirteen millimeters per side, resulting in crowding of the solder bumps along the perimeter of the flip chip. Consequently, flip chip conductor patterns are typically composed of numerous individual conductors that are often spaced apart about 0.1 millimeter or less.
A section of a typical conventional flip chip 26 is shown schematically in FIG. 1 and includes a solder bump 10 which is soldered directly to the continuous upper surface of a bump pad 14, typically rectangular in configuration, as shown in FIG. 1A, and partially covered by a passivation layer 12. A circular pad opening 13 in the passivation layer 12 exposes the bump pad 14, through which pad opening 13 the solder bump 10 extends. The bump pad 14 is surrounded by a dielectric layer 15 such as an oxide in the chip 26. As further shown in FIG. 1, the bump pad 14 is provided in electrical contact with an upper conductive layer 16, which is separated from an underlying conductive layer 22 by an insulative layer 18. The conductive layers 16, 22 are disposed in electrical contact with each other through conductive vias 20 that extend through the insulative layers 18. The various insulative layers 18 and conductive layers 22 are sequentially deposited on a silicon substrate 24 throughout semiconductor fabrication, in conventional fashion. After the solder bumps 10 are formed on the flip chip 26, the chip 26 is inverted (thus the term, xe2x80x9cflip chipxe2x80x9d) and the solder bumps 10 are bonded to electrical terminals in a substrate (not shown) such as a printed circuit board.
After the solder bumps 10 are bonded to the substrate, the flip chip 26 is subjected to a variety of tests such as, for example, bump shear tests and die shear tests, in which shear stress is applied to the chip to determine the mechanical integrity of the electrical connections between the chip and the bonded substrate. The continuous surface of the bump pad, to which the solder bump adheres, has been found to provide unsatisfactory bonding characteristics of the solder bump to the chip, as revealed by shear tests, since the solder bumps tend to break off from the bump pads upon subjecting the solder bumps to a relatively low threshold value of shear stress. Accordingly, it has been found that providing multiple apertures in the bump pad significantly strengthens the mechanical bond between the solder bump and the bump pad. It has further been found that increasing the number of corners of the bump pad beyond four, in the case of the rectangular bump pad 14 shown in FIG. 1A, enhances the stress distribution characteristics of the bump pads in the dielectric layer of the chip when the solder bumps are subjected to shear stress. This, in turn, strengthens the mechanical interconnection between the flip chip and the substrate to which the chip is bonded. Accordingly, a new and improved design for flip chip bump pads is needed to strengthen the mechanical association between flip chip solder bumps and the bump pads on the chip, as well as to enhance the stress distribution characteristics of the bump pads in the chip.
An object of the present invention is to provide new and improved solder bump pads which contribute to stronger mechanical association between the solder bump pads and solder bumps on a chip.
Another object of the present invention is to provide bump pads which are used in the assembly of flip chips.
Another embodiment of the present invention is to provide new and improved solder bump pads which enhance the distribution of stress applied to the pads through solder bumps on the pads in order to facilitate stronger mechanical association between the pads and the solder bumps.
Still another embodiment of the present invention is to provide multi-apertured solder bump pads which enhance bonding of solder bumps to the pads.
Another object of the present invention is to provide solder bump pads which may be characterized by a non-continuous bonding surface.
Yet another object of the present invention is to provide solder bump pads which may be shaped in the configuration of a polygon having eight or more corners.
A still further object of the present invention is to provide solder bump pads which may be provided with interlock fingers for interlocking with adjacent layers in a chip.
Yet another object of the present invention is to provide solder bump pads each having corners of less than, equal to or greater than ninety degrees.
In accordance with these and other objects and advantages, the present invention is directed to bump pads particularly for flip chips in the packaging of semiconductor integrated circuits. The bump pads are each polygon-shaped and may be provided with multiple bonding apertures, in the form of slots or openings, to improve adhesion of solder bumps to the pads in the assembly of the flip chips. The edges of the flip chip may be provided with multiple interlock fingers and interlock slots which mate with respective interlock slots and fingers in the dielectric layer surrounding the pad in the chip. The mating interlock fingers and slots tend to improve adhesion of the bump pad with the dielectric layer in the chip. Preferably, but not necessarily, the bump pads have at least eight corners each having an angle of greater than ninety degrees. The multiple corners facilitate a greater stress distribution area on the bump pads against the surrounding dielectric layer, and this tends to stabilize the bump pads in the chip upon application of shear stress to the solder bumps on the bump pads.
In one embodiment of the invention, the bump pad includes a continuous or solid central region which is at least partially surrounded by an inner set of openings. An outer set of openings surrounds the inner set of openings adjacent to the perimeter of the bump pad. In another embodiment, the openings may be circular and are more or less evenly distributed throughout the entire area of the bump pad. In still another embodiment, the bump pad includes multiple slots which extend across the width of the pad and are separated by bands. Any of the apertured embodiments of the bump pad may include the interlock fingers and slots for stabilizing the bond pad in the chip. Further, any of the apertured embodiments of the bump pad may have any number of corners each having an angle of less than, equal to or greater than ninety degrees. Each of the bump pads may have either a one-layered or a two-layered construction.